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	I(2)C-bus Design Based on FPGA
	Cao, Da ; Wu, Shunxiang ; Su, Longjiang ; Wu SX(吴顺祥)
	2011
英文摘要	Conference Name:International Conference on Materials Science and Engineering Science. Conference Address: Shenzhen, PEOPLES R CHINA. Time:DEC 11-12, 2010.; Introduced field programmable gate array FPGA with I(2)C bus interface device interface design. Programming with VHDL, using general FPGA I/O port to generate I2C bus interface signal timing, achieved FPGA with I(2)C-bus devices data communication, went through the simulation test, given the application example of FPGA with I(2)C-bus EEPROOM chip AT24C02 connected hardware design.
语种	英语
出处	http://dx.doi.org/10.4028/www.scientific.net/AMR.179-180.528
出版者	ADV MATER RES-SWITZ
内容类型	其他
源URL	[http://dspace.xmu.edu.cn/handle/2288/86486]
专题	信息技术－会议论文
推荐引用方式 GB/T 7714	Cao, Da,Wu, Shunxiang,Su, Longjiang,et al. I(2)C-bus Design Based on FPGA. 2011-01-01.

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