POSE: Design of Hardware-Friendly Particle-Based Observation Selection PHD Filter

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	POSE: Design of Hardware-Friendly Particle-Based Observation Selection PHD Filter
	Shi, Zhiguo ; Liu, Yongkang ; Hong, Shaohua ; Chen, Jiming ; Shen, Xuemin Sherman ; Hong SH(洪少华)
刊名	http://dx.doi.org/10.1109/TIE.2013.2262753
	2014
关键词	MULTIPLE-TARGET TRACKING ALGORITHM EFFICIENT SURVEILLANCE ARCHITECTURE NETWORKS SYSTEMS
英文摘要	National Science Foundation of China [61171149]; Research Foundation of the Chinese State Key Laboratory of Industrial Control Technology [ICT1119, NCET-11-0445, 2011AA040101-1]; Fundamental Research Funds for the Chinese Central Universities [2013xzzx008-2]; Ontario Research Fund-Research Excellence (ORF-RE), Ontario, Canada; Particle probability hypothesis density (PHD) filtering is a promising technology for the multitarget-tracking problem. Traditional particle PHD filter solutions usually have high computational complexity, and the lack of dedicated hardware has seriously limited their usages in real-time industrial applications. The hardware implementation difficulty of the particle PHD filtering in field-programmable gate array (FPGA) platforms lies in that the number of observations for filtering is time varying while the number of parallel processing units in circuit is fixed. To overcome this challenge, we propose a novel particle-based observation selection (POSE) PHD filter algorithm and its hardware implementation in this paper. Specifically, we opportunistically select a fixed number of observations out of a varying number of observations for filtering, where the approximation error is proved to be negligible by adapting the circuit budget to the environment accordingly. To implement the proposed POSE PHD filter, the hardware design issues are addressed in depth. Extensive simulations demonstrate that the POSE PHD filter has a comparable performance with the traditional one while its hardware implementation challenge is overcome. The hardware experiment results of the POSE PHD filter on a Xilinx Virtex-II Pro FPGA platform match the simulation ones well. Furthermore, the execution time of the implemented hardware circuit is evaluated, and the results show that it can achieve a processing rate of 6.892 kHz with a 50-MHz system clock.
语种	英语
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
内容类型	期刊论文
源URL	[http://dspace.xmu.edu.cn/handle/2288/92712]
专题	信息技术－已发表论文
推荐引用方式 GB/T 7714	Shi, Zhiguo,Liu, Yongkang,Hong, Shaohua,et al. POSE: Design of Hardware-Friendly Particle-Based Observation Selection PHD Filter[J]. http://dx.doi.org/10.1109/TIE.2013.2262753,2014.
APA	Shi, Zhiguo,Liu, Yongkang,Hong, Shaohua,Chen, Jiming,Shen, Xuemin Sherman,&洪少华.(2014).POSE: Design of Hardware-Friendly Particle-Based Observation Selection PHD Filter.http://dx.doi.org/10.1109/TIE.2013.2262753.
MLA	Shi, Zhiguo,et al."POSE: Design of Hardware-Friendly Particle-Based Observation Selection PHD Filter".http://dx.doi.org/10.1109/TIE.2013.2262753 (2014).