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	A 14-bit 500-MS/s DAC with digital background calibration
	Xu Z(徐震) ; Li XQ(李学清) ; Liu JN(刘嘉男) ; Wei Q(魏琦) ; Luo L(骆丽) ; Yang HZ(杨华中) ; Xu Zhen ; Li Xueqing ; Liu Jia'nan ; Wei Qi ; Luo Li ; Yang Huazhong
	2016-03-30 ; 2016-03-30
关键词	digital to analog converter(DAC) current-steering digital background calibration TN792
其他题名	A 14-bit 500-MS/s DAC with digital background calibration
中文摘要	Thelinearityofcurrent-steeringdigital-to-analogconverters(DACs)atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matching. This, however, results in large gradient errors and parasitic capacitance, which degrade the spurious free dynamic range(SFDR) for high-frequency signals. To overcome this problem, calibration is an effective method.In this paper, a digital background calibration technique for current-steering DACs is presented and verified by a 14-bit DAC in a 0.13 m standard CMOS process. The measured differential nonlinearity(DNL) and integral nonlinearity(INL) are 0.4 LSB and 1.2 LSB, respectively. At 500-MS/s, the SFDR is 70 dB and 50.3 dB for signals of 5.4 MHz and 224 MHz, respectively. The core area is 0.69 mm2and the power consumption is 165 mW from a mixed power supply with 1.2 V and 3.3 V.; Thelinearityofcurrent-steeringdigital-to-analogconverters(DACs)atlowsignalfrequenciesismainly limited by matching properties of current sources, so large-size current source arrays are widely used for better matching. This, however, results in large gradient errors and parasitic capacitance, which degrade the spurious free dynamic range(SFDR) for high-frequency signals. To overcome this problem, calibration is an effective method.In this paper, a digital background calibration technique for current-steering DACs is presented and verified by a 14-bit DAC in a 0.13 m standard CMOS process. The measured differential nonlinearity(DNL) and integral nonlinearity(INL) are 0.4 LSB and 1.2 LSB, respectively. At 500-MS/s, the SFDR is 70 dB and 50.3 dB for signals of 5.4 MHz and 224 MHz, respectively. The core area is 0.69 mm2and the power consumption is 165 mW from a mixed power supply with 1.2 V and 3.3 V.
语种	英语 ; 英语
内容类型	期刊论文
源URL	[http://ir.lib.tsinghua.edu.cn/ir/item.do?handle=123456789/146613]
专题	清华大学
推荐引用方式 GB/T 7714	Xu Z,Li XQ,Liu JN,et al. A 14-bit 500-MS/s DAC with digital background calibration[J],2016, 2016.
APA	徐震.,李学清.,刘嘉男.,魏琦.,骆丽.,...&Yang Huazhong.(2016).A 14-bit 500-MS/s DAC with digital background calibration..
MLA	徐震,et al."A 14-bit 500-MS/s DAC with digital background calibration".(2016).

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