QQ客服 官方微博 反馈留言

	Optimization and hardware implementation of H.264/AVC luma interpolation
	Yang Kun ; Zhang Chun ; Wang Zhi-hua
	2010-10-12 ; 2010-10-12
关键词	Practical/ video coding/ hardware implementation H.264-AVC luma interpolation uniform interpolation process parallel calculation unit memory access unit local memory pipe-line technology CIF video stream CMOS process frequency 5.7 MHz size 0.18 mum/ B6135C Image and video coding C5260D Video signal processing/ frequency 5.7E+06 Hz size 1.8E-07 m
中文摘要	A uniform interpolation process and its hardware implementation solution are proposed in this paper. By introducing parallel calculation unit, memory access unit, local memory and pipe-line technology, it will take the proposed design 5.7 MHz working frequency to achieve the interpolation process for a 30 f/s(frame/second) CIF video stream. The speed of the proposed circuit is 26 times of a pure software implementation. The decoder is fabricated in 0.18 mu m CMOS process. The interpolation hardware consists of 35*10/sup 3/ gates.
语种	中文
出版者	Beijing TV and Audio Engineering Publishing House ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/82582]
专题	清华大学
推荐引用方式 GB/T 7714	Yang Kun,Zhang Chun,Wang Zhi-hua. Optimization and hardware implementation of H.264/AVC luma interpolation[J],2010, 2010.
APA	Yang Kun,Zhang Chun,&Wang Zhi-hua.(2010).Optimization and hardware implementation of H.264/AVC luma interpolation..
MLA	Yang Kun,et al."Optimization and hardware implementation of H.264/AVC luma interpolation".(2010).

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。