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	Design networks-on-chip with latency/bandwidth guarantees
	Lin, S. ; Su, L. ; Su, H. ; Zhou, G. ; Jin, D. ; Zeng, L.
	2010-10-12 ; 2010-10-12
关键词	Practical/ circuit switching logic design network interfaces network-on-chip/ network-on-chip design traffic classification flit-based switching link bandwidth setting network interface router/ B1265F Microprocessors and microcomputers B1265A Digital circuit design, modelling and testing C5130 Microprocessor chips C5210 Logic design methods
中文摘要	A method is proposed to guarantee bandwidth (BW) or latency of network-on-chip. This method contains three kernels: traffic classification; flit-based switching; path pre-assignment and link-BW setting. Compared with the traditional circuit-switch method, the proposed method can guarantee the latency between one flit's generation in the source node and its reception in the destination node. This method also supports a wide range of traffic types such as latency critical, low BW traffic and streaming data which only have BW requirement. Moreover, router and network interface which support the proposed method are implemented and a maximum latency formula is developed. Simulation and synthesis results show that this method can guarantee the BW and latency well and is relatively low cost.
语种	英语
出版者	IET ; UK
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/82327]
专题	清华大学
推荐引用方式 GB/T 7714	Lin, S.,Su, L.,Su, H.,et al. Design networks-on-chip with latency/bandwidth guarantees[J],2010, 2010.
APA	Lin, S.,Su, L.,Su, H.,Zhou, G.,Jin, D.,&Zeng, L..(2010).Design networks-on-chip with latency/bandwidth guarantees..
MLA	Lin, S.,et al."Design networks-on-chip with latency/bandwidth guarantees".(2010).

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