| 重叠组合法的芯片级三维寄生电容提取及其并行实现 | |
| 尹航 ; 喻文健 ; 陆涛涛 ; 王泽毅 ; Yin Hang ; Yu Wenjian ; Lu Taotao ; Wang Zeyi | |
| 2010-06-09 ; 2010-06-09 | |
| 关键词 | 边界元法 三维寄生电容 芯片级提取 重叠组合 并行计算 boundary element method 3D parasitic capacitance chip-level extraction overlap-combination parallel computing TN47 |
| 其他题名 | The Overlap-Combination Approach to 3D Chip-Level Capacitance Extraction and Its Parallel Implementation |
| 中文摘要 | 采用双向区域重叠组合法,基于三维层次式块边界元法实现了芯片级的互连电容提取·该方法将芯片切分为大量小规模区域,用全局场求解器计算各子区域电容矩阵,可方便地组合出整个芯片的电容矩阵;同时分析了其计算量和精度,并进行了并行计算实验·对实际版图结构的数值实验验证了有关分析结论,表明该方法高效、可靠、并行性能好·; A two-direction overlap-combination method is adopted to implement the chip-level capacitance extraction while using the 3D hierarchical block boundary element method as field solver. The proposed method cuts a chip into a great deal of small-scale regions, and then combines the capacitance matrices for all regions to get the full capacitance matrix. The computational accuracy and speed of the overlap-combination method are also analyzed, and parallel experiments were carried out. Numerical experiments with actual layout structures show that the proposed method is effective, reliable and with high parallelity.; 国家自然科学基金(90407004); 国家“八六三”高技术研究发展计划(2004AA1Z1050) |
| 语种 | 中文 ; 中文 |
| 内容类型 | 期刊论文 |
| 源URL | [http://hdl.handle.net/123456789/55839]  |
| 专题 | 清华大学 |
| 推荐引用方式 GB/T 7714 | 尹航,喻文健,陆涛涛,等. 重叠组合法的芯片级三维寄生电容提取及其并行实现[J],2010, 2010. |
| APA | 尹航.,喻文健.,陆涛涛.,王泽毅.,Yin Hang.,...&Wang Zeyi.(2010).重叠组合法的芯片级三维寄生电容提取及其并行实现.. |
| MLA | 尹航,et al."重叠组合法的芯片级三维寄生电容提取及其并行实现".(2010). |
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