| 模拟集成电路三维互连电容的改进层次式提取 | |
| 李漓 ; 喻文健 ; 王泽毅 ; 洪先龙 ; Li Li ; Yu Wenjian ; Wang Zeyi ; Hong Xianlong | |
| 2010-06-09 ; 2010-06-09 | |
| 关键词 | 寄生电容 边界元法 层次式算法 模拟集成电路 parasitic capacitance boundary element hierarchical computation analog integrated circuit TN432 |
| 其他题名 | Improved Hierarchical Extraction of 3D Interconnect Capacitance in Analog Integrated Circuits |
| 中文摘要 | 层次式直接边界元方法可一次性计算出整个互连寄生电容矩阵,具有较高的计算效率针对模拟集成电路的特点,对层次式三维电容提取的三维块切割方式、非均匀边界元划分和程序组织等方面进行了改进,显著地提高了算法的效率数值实验表明,改进的层次式互连电容提取在保证高精度的同时,速度提高了数倍,适用于实际的模拟集成电路设计; The hierarchical block boundary element method is highly efficient by its once computation to extract the whole interconnect capacitance matrix. In analog integrated circuit layout, the feature size varies largely with different layers. According to this, we present an improved algorithm in this paper, including a new hierarchical partition method of 3D blocks, nonuniform subdivision of boundary elements, and optimization of algorithm organization. Numerical results show that the new algorithm is suitable for real analog integrated circuit layout, in an improvement under equal accuracy, a few times faster than the previous approach.; 国家自然科学基金(60401010,90407004); 国家“八六三”高技术研究发展计划(2004AA1Z1050) |
| 语种 | 中文 ; 中文 |
| 内容类型 | 期刊论文 |
| 源URL | [http://hdl.handle.net/123456789/55142]  |
| 专题 | 清华大学 |
| 推荐引用方式 GB/T 7714 | 李漓,喻文健,王泽毅,等. 模拟集成电路三维互连电容的改进层次式提取[J],2010, 2010. |
| APA | 李漓.,喻文健.,王泽毅.,洪先龙.,Li Li.,...&Hong Xianlong.(2010).模拟集成电路三维互连电容的改进层次式提取.. |
| MLA | 李漓,et al."模拟集成电路三维互连电容的改进层次式提取".(2010). |
| 个性服务 |
| 查看访问统计 |
| 相关权益政策 |
| 暂无数据 |
| 收藏/分享 |
除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。
修改评论