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	VLSI architecture of EBCOT encoder for JPEG2000
	Liu Lei-bo ; Li De-jian ; Meng Hong-ying ; Zhang Li ; Wang Zhi-hua ; Chen Hong-yi ; Xia Yu-wen
	2010-05-07 ; 2010-05-07
关键词	Practical Theoretical or Mathematical/ data compression parallel architectures video coding VLSI wavelet transforms/ VLSI architecture EBCOT dynamic memory control DMC on-chip wavelet coefficients storage parallel architecture coding process IP core JPEG2000 real-time image application real-time video application/ B6135C Image and video coding B2570 Semiconductor integrated circuits B0290X Integral transforms in numerical analysis C5260D Video signal processing C5220P Parallel architecture
中文摘要	Proposes a VLSI architecture of EBCOT, in which a dynamic memory control (DMC) is adopted to reduce 60% scale of the on-chip wavelet coefficients storage. A parallel architecture is proposed to speed-up the coding process. This architecture can be used as a compact and efficient IP core for JPEG2000 VLSI implementation and various real-time image/video applications.
语种	中文 ; 中文
出版者	Beijing Univ. of Posts and Telecommunications ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/16724]
专题	清华大学
推荐引用方式 GB/T 7714	Liu Lei-bo,Li De-jian,Meng Hong-ying,et al. VLSI architecture of EBCOT encoder for JPEG2000[J],2010, 2010.
APA	Liu Lei-bo.,Li De-jian.,Meng Hong-ying.,Zhang Li.,Wang Zhi-hua.,...&Xia Yu-wen.(2010).VLSI architecture of EBCOT encoder for JPEG2000..
MLA	Liu Lei-bo,et al."VLSI architecture of EBCOT encoder for JPEG2000".(2010).

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