QQ客服 官方微博 反馈留言

	A high linearity, 13 bit pipelined CMOS ADC
	Li Fule ; Duan Jingbo ; Wang Zhihua
	2010-05-07 ; 2010-05-07
关键词	Practical/ analogue-digital conversion bootstrap circuits capacitors CMOS integrated circuits operational amplifiers/ pipelined CMOS ADC high linearity pipelined analog-to-digital converter passive capacitor error capacitor mismatch error gain-boosting opamp finite gain error gain nonlinearity bootstrapping switch power dissipation size 0.18 mum word length 13 bit voltage 2.7 V/ B1265H A/D and D/A convertors B1220 Amplifiers B2130 Capacitors B2570D CMOS integrated circuits C5180 A/D and D/A convertors/ size 1.8E-07 m word length 1.3E+01 bit voltage 2.7E+00 V
中文摘要	A 13 bit, pipelined analog-to-digital converter (ADC) designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity, a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18 mu m CMOS technology and occupies a die area of 3.2 mm/sup 2/ including pads. Measured performance includes -0.18/ 0.15 LSB of differential nonlinearity, - 0.35/0.5 LSB of integral nonlinearity, 75.7 dB of signal-to-noise plus distortion ratio (SNDR) and 90.5 dBc of spurious-free dynamic range (SFDR) for 2.4 MHz input at 2.5 MS/s. At full speed conversion (5 MS/s) and for the same 2.4 MHz input, the measured SNDR and SFDR are 73.7 dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21 mW at 2.5 MS/s and 34 mW at 5 MS/s,both at 2.7 V supply.
语种	中文 ; 中文
出版者	Science Press ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/16585]
专题	清华大学
推荐引用方式 GB/T 7714	Li Fule,Duan Jingbo,Wang Zhihua. A high linearity, 13 bit pipelined CMOS ADC[J],2010, 2010.
APA	Li Fule,Duan Jingbo,&Wang Zhihua.(2010).A high linearity, 13 bit pipelined CMOS ADC..
MLA	Li Fule,et al."A high linearity, 13 bit pipelined CMOS ADC".(2010).

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。