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	A CMOS high-speed sample-and-hold amplifier
	Xue Liang ; Shen Yan-Zhao ; Zhang Xiang-Min
	2010-05-07 ; 2010-05-07
关键词	Practical Theoretical or Mathematical/ analogue-digital conversion bootstrap circuits circuit simulation CMOS integrated circuits high-speed integrated circuits operational amplifiers sample and hold circuits SPICE/ CMOS high speed amplifier sample and hold amplifier sampling rate TSMC standard CMOS process Hspice ADC bootstrap circuits 0.35 micron/ B1290 Other analogue circuits B2570D CMOS integrated circuits B1130B Computer-aided circuit analysis and design B2570A Semiconductor integrated circuit design, layout, modelling and testing B1220 Amplifiers B1265H A/D and D/A convertors C5330 Analogue storage C7410D Electronic engineering computing C5180 A/D and D/A convertors/ size 3.5E-07 m
中文摘要	The fundamental theory of the sample and hold circuit is analyzed, and a CMOS high-speed sample-and-hold amplifier is designed, for which a sampling rate of 50 Msample/s has been achieved. The circuit, as well as its blocks, is simulated, in TSMC 's 0.35 mu m standard CMOS process using Hspice.
语种	中文 ; 中文
出版者	Editorial Dept. Microelectronics ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/16491]
专题	清华大学
推荐引用方式 GB/T 7714	Xue Liang,Shen Yan-Zhao,Zhang Xiang-Min. A CMOS high-speed sample-and-hold amplifier[J],2010, 2010.
APA	Xue Liang,Shen Yan-Zhao,&Zhang Xiang-Min.(2010).A CMOS high-speed sample-and-hold amplifier..
MLA	Xue Liang,et al."A CMOS high-speed sample-and-hold amplifier".(2010).

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