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	Low power 13 bit 10/sup 7/ sample/s A/D converter
	Li Fule ; Wang Hongmei ; Li Dongmei ; Wang Zhihua
	2010-05-07 ; 2010-05-07
关键词	Practical Theoretical or Mathematical/ analogue-digital conversion CMOS integrated circuits convertors Monte Carlo methods operational amplifiers sample and hold circuits/ pipelined analog-to-digital converter CMOS technology capacitor error averaging technique operational amplifier sharing sample-and-hold amplifier cancellation dynamic comparator transistor-level Monte-Carlo simulation 1 MHz 10 MHz 82 dB/ B1265H A/D and D/A convertors B1290B Convertors B1220 Amplifiers B0240G Monte Carlo methods/ frequency 1.0E+06 Hz frequency 1.0E+07 Hz noise figure 8.2E+01 dB
中文摘要	The design of a low-power 13 bit, 10/sup 7/ sample/s pipelined analog-to-digital converter (ADC) in 0.6 mu m CMOS technology was described. The capacitor error averaging technique was used to achieve the 13 bit precision, with circuit techniques such as operational amplifier sharing, input sample-and-hold amplifier cancellation, and dynamic comparator used to reduce the power. Technology non-idealities were included in a transistor-level Monte-Carlo simulation of the ADC. Simulation results show that a free dynamic range of 82 dB is achieved for an input of 1 MHz at a full speed of 10 MHz while consuming only 11 mW of power in the analog section.
语种	中文 ; 中文
出版者	Tsinghua Univ. Press ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/16389]
专题	清华大学
推荐引用方式 GB/T 7714	Li Fule,Wang Hongmei,Li Dongmei,et al. Low power 13 bit 10/sup 7/ sample/s A/D converter[J],2010, 2010.
APA	Li Fule,Wang Hongmei,Li Dongmei,&Wang Zhihua.(2010).Low power 13 bit 10/sup 7/ sample/s A/D converter..
MLA	Li Fule,et al."Low power 13 bit 10/sup 7/ sample/s A/D converter".(2010).

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