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	Energy recovery threshold logic
	Yang Qian ; Zhou Runde
	2010-05-07 ; 2010-05-07
关键词	Practical/ CMOS logic circuits integrated circuit design logic circuits threshold logic/ energy recovery threshold logic power dissipation gate complexity carry lookahead adder CMOS circuits Hspice simulation 3 V 5 V/ B2570D CMOS integrated circuits B1265B Logic circuits B2570A Semiconductor integrated circuit design, layout, modelling and testing B1265A Digital circuit design, modelling and testing/ voltage 3.0E+00 V voltage 5.0E+00 V
中文摘要	A new energy recovery logic style (energy recovery threshold logic, ERTL) based on threshold logic is presented. With threshold logic, ERTL has very low power dissipation and low gate complexity. A 4-bit ERTL carry lookahead adder (CLA) and static CMOS CLA which are designed respectively with the same architecture. The transistor counts of ERTL CLA logic circuits is only 63% of static CMOS CLA. Compared to previous energy recovery logic designs, ERTL has low hardware cost. The adders are designed using 0.35 mu m TSMC CMOS technology. The circuit is simulated at 3 V and 5 V. Based on the results of Hspice simulation, for a practical load and a practical range of frequencies, ERTL dissipates only 14%~58% of the energy of the static CMOS.
语种	中文 ; 中文
出版者	Science Press ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/16367]
专题	清华大学
推荐引用方式 GB/T 7714	Yang Qian,Zhou Runde. Energy recovery threshold logic[J],2010, 2010.
APA	Yang Qian,&Zhou Runde.(2010).Energy recovery threshold logic..
MLA	Yang Qian,et al."Energy recovery threshold logic".(2010).

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