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	Super wide-range variable-rate timing recovery scheme and implementation
	Liu Qi-jia ; Pan Chang-yong ; Zhang Guo-jing
	2010-05-06 ; 2010-05-06
关键词	Practical Theoretical or Mathematical/ direct digital synthesis phase detectors quadrature phase shift keying satellite communication signal processing synchronisation time-domain analysis timing jitter/ multirate satellite signal variable-rate digital timing recovery QPSK signal direct digital synthesizer DPLL lead-lag phase detector time-domain analysis timing jitter reduction/ B6250G Satellite communication systems B6140 Signal processing and detection B6120 Modulation and coding methods B0220 Mathematical analysis
中文摘要	To investigate the reception of multi-rate satellite signals, a super wide-range variable-rate digital timing recovery algorithm is proposed, which is suitable for QPSK signals with rates ranging from 20 Mbps to 320 Mbps. Based on the direct digital synthesizer (DDS), the algorithm uses the structure of DPLL comprised of lead-lag phase detector for timing recovery. Furthermore, new methods derived from time-domain analysis are presented to widen the acquisition range and reduce timing jitter. Simulation and implementation results show the super wide acquisition range and good timing-jitter performance under practical conditions.
语种	中文 ; 中文
出版者	Science Press ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/12058]
专题	清华大学
推荐引用方式 GB/T 7714	Liu Qi-jia,Pan Chang-yong,Zhang Guo-jing. Super wide-range variable-rate timing recovery scheme and implementation[J],2010, 2010.
APA	Liu Qi-jia,Pan Chang-yong,&Zhang Guo-jing.(2010).Super wide-range variable-rate timing recovery scheme and implementation..
MLA	Liu Qi-jia,et al."Super wide-range variable-rate timing recovery scheme and implementation".(2010).

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