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	Buffering high-speed packets with tri-stage memory array and its performance analysis
	Wang Peng ; Yi Pen ; Jin De-Peng ; Zeng Lie-Guang
	2010-05-06 ; 2010-05-06
关键词	Practical/ buffer storage packet switching performance evaluation telecommunication network routing/ tri-stage memory array performance analysis routers switches packet buffers memory management/ B6150C Communication switching B6150P Communication network design, planning and routing B1265D Memory circuits C5620 Computer networks and techniques C5320G Semiconductor storage C5670 Network performance
中文摘要	High-performance routers and switches need large throughput packet buffers to hold packets. However, the technique of commercially available memories is limited and can hardly fulfil this high throughput packet buffers. As a result, the development of networks is restricted severely. This paper presents a tri-stage memory array architecture to solve the problem, which can accomplish the arbitrary high-speed packet buffer theoretically. It is proved that the critical queue first algorithm can be applied as the memory management algorithm to get zero delay scheduling as well as minimum scale system. Furthermore, the design of hardware implementation architecture of the tri-stage memory array system is provided finally.
语种	中文 ; 中文
出版者	Science Press ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/11941]
专题	清华大学
推荐引用方式 GB/T 7714	Wang Peng,Yi Pen,Jin De-Peng,et al. Buffering high-speed packets with tri-stage memory array and its performance analysis[J],2010, 2010.
APA	Wang Peng,Yi Pen,Jin De-Peng,&Zeng Lie-Guang.(2010).Buffering high-speed packets with tri-stage memory array and its performance analysis..
MLA	Wang Peng,et al."Buffering high-speed packets with tri-stage memory array and its performance analysis".(2010).

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