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	A generic programmable dual modulus divider
	Huang Shuilong ; Wang Zhihua
	2010-05-06 ; 2010-05-06
关键词	Practical/ CMOS integrated circuits counting circuits direct digital synthesis dividing circuits phase locked loops prescalers sigma-delta modulation trigger circuits/ generic programmable dual modulus divider prescaler 8-bit programmable counter Sigma Delta modulator swallow pulse divider true-single-phase-clocking dynamic TSPC trigger digital synthesis-placing-routing 0.18 mu m 1.8 V CMOS technology SpectreVerilog simulation phase locked loop PLL frequency synthesizer 0.18 micron 1.8 V 2 GHz/ B1265B Logic circuits B1265H A/D and D/A convertors B1260 Pulse circuits B2570D CMOS integrated circuits B1250 Modulators, demodulators, discriminators and mixers/ size 1.8E-07 m voltage 1.8E+00 V frequency 2.0E+09 Hz
中文摘要	A programmable dual modulus divider is proposed. The circuit mainly includes three building blocks: prescaler, 8-bit programmable counter and Sigma Delta modulator. Two operation modes (integer/fractional-N) are achieved by switching on/off the output signal of the Sigma Delta modulator. Only a programmable counter is needed for the swallow pulse divider. The prescaler was designed by using the improved dynamic TSPC triggers, and the other blocks were realized by the way of digital synthesis, placing and routing. Based on 0.18 mu m 1.8 V CMOS technology, SpectreVerilog simulations verify that it can operate within the division ratio of 56-2 047 with 2 GHz maximum operation frequency and <4 mA current dissipation. The circuit is very simple and can be used in the high performance PLL frequency synthesizer.
语种	中文 ; 中文
出版者	Peking University Press ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/10600]
专题	清华大学
推荐引用方式 GB/T 7714	Huang Shuilong,Wang Zhihua. A generic programmable dual modulus divider[J],2010, 2010.
APA	Huang Shuilong,&Wang Zhihua.(2010).A generic programmable dual modulus divider..
MLA	Huang Shuilong,et al."A generic programmable dual modulus divider".(2010).

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