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	Hiding memory access latency in software pipelining
	Liu Li ; Li Wen-Long ; Chen Yu ; Li Sheng-Mei ; Tang Zhi-Zhong
	2010-05-06 ; 2010-05-06
关键词	Practical/ pipeline processing processor scheduling program control structures storage management/ hiding memory access latency software pipelining memory optimization technologies foresighted latency modulo scheduling load instructions/ C6150N Distributed systems software C6120 File organisation C6150C Compilers, interpreters and other processors
中文摘要	Software pipelining tries to improve the performance of a loop by overlapping the execution of several successive iterations. As processor gets much higher speed, the memory access latency becomes a bottleneck that restricts higher performance. Software pipelining has been combined with several memory optimization technologies for higher performance by hiding memory access latency. This paper presents a foresighted latency modulo scheduling (FLMS) algorithm which determines the latency of load instructions according to the feature of the loop. Experimental results show that FLMS decreases the stall time and improves the performance of programs.
语种	中文 ; 中文
出版者	Science Press ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/10335]
专题	清华大学
推荐引用方式 GB/T 7714	Liu Li,Li Wen-Long,Chen Yu,et al. Hiding memory access latency in software pipelining[J],2010, 2010.
APA	Liu Li,Li Wen-Long,Chen Yu,Li Sheng-Mei,&Tang Zhi-Zhong.(2010).Hiding memory access latency in software pipelining..
MLA	Liu Li,et al."Hiding memory access latency in software pipelining".(2010).

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