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	An overview of integrating high level synthesis and floorplan
	Wang Yunfeng ; Liu Zhipeng ; Bian Jinian
	2010-05-06 ; 2010-05-06
关键词	Practical Theoretical or Mathematical/ circuit complexity delay circuits electronic design automation high level synthesis integrated circuit manufacture power consumption/ high level synthesis floorplan electronic design automation IC fabrication technology IC chips power consumption interconnect delay/ B1130B Computer-aided circuit analysis and design B1265A Digital circuit design, modelling and testing C7410D Electronic engineering computing C5210B Computer-aided logic design C4240C Computational complexity
中文摘要	The research on "integrating high level synthesis and floorplan" is a very important part in the research on electronic design automation. In this paper, the current research status of this field is introduced, and the basic methodologies and algorithms are also presented. These methodologies and algorithms are mainly focused on the following two problems, which are caused by the rapid development of IC fabrication technology. Firstly, with the fast increasing of the complexity of IC chips, it is necessary to start a design at a higher abstraction level. Secondly, as the feature size of IC keeps on shrinking into the nanometer level, physical effects have been playing a dominant role in final delay and power consumption of a circuit. In this paper, the typical algorithms of the 90 s of last century are described, and the basic principles of these algorithms are also analyzed and summarized.
语种	中文 ; 中文
出版者	Science Press ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/10275]
专题	清华大学
推荐引用方式 GB/T 7714	Wang Yunfeng,Liu Zhipeng,Bian Jinian. An overview of integrating high level synthesis and floorplan[J],2010, 2010.
APA	Wang Yunfeng,Liu Zhipeng,&Bian Jinian.(2010).An overview of integrating high level synthesis and floorplan..
MLA	Wang Yunfeng,et al."An overview of integrating high level synthesis and floorplan".(2010).

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