The overlap-combination approach to 3D chip-level capacitance extraction and its parallel implementation | |
Yin Hang ; Yu Wenjian ; Lu Taotao ; Wang Zeyi | |
2010-05-06 ; 2010-05-06 | |
关键词 | Practical Theoretical or Mathematical/ boundary-elements methods capacitance integrated circuit layout logic CAD parallel processing/ 3D chip-level capacitance extraction two-direction overlap-combination method 3D hierarchical block boundary element method field solver capacitance matrix 3D parasitic capacitance parallel computing/ B1130B Computer-aided circuit analysis and design B1265A Digital circuit design, modelling and testing B0290T Finite element analysis C7410D Electronic engineering computing C6150N Distributed systems software C4185 Finite element analysis C5210B Computer-aided logic design |
中文摘要 | A two-direction overlap-combination method is adopted to implement the chip-level capacitance extraction while using the 3D hierarchical block boundary element method as field solver. The proposed method cuts a chip into a great deal of small-scale regions, and then combines the capacitance matrices for all regions to get the full capacitance matrix. The computational accuracy and speed of the overlap-combination method are also analyzed, and parallel experiments were carried out. Numerical experiments with actual layout structures show that the proposed method is effective, reliable and with high parallelity. |
语种 | 中文 ; 中文 |
出版者 | Science Press ; China |
内容类型 | 期刊论文 |
源URL | [http://hdl.handle.net/123456789/9926] ![]() |
专题 | 清华大学 |
推荐引用方式 GB/T 7714 | Yin Hang,Yu Wenjian,Lu Taotao,et al. The overlap-combination approach to 3D chip-level capacitance extraction and its parallel implementation[J],2010, 2010. |
APA | Yin Hang,Yu Wenjian,Lu Taotao,&Wang Zeyi.(2010).The overlap-combination approach to 3D chip-level capacitance extraction and its parallel implementation.. |
MLA | Yin Hang,et al."The overlap-combination approach to 3D chip-level capacitance extraction and its parallel implementation".(2010). |
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