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	Virtual delay vector-based core-stateless packet scheduling architecture
	Qin Yan ; Xiang Yong ; Shi Meilin
	2010-05-06 ; 2010-05-06
关键词	Practical Theoretical or Mathematical/ bandwidth allocation computer networks delays packet switching resource allocation scheduling telecommunication traffic/ traffic flow virtual delay vector technique core-stateless packet scheduling end-to-end delay virtual clock rate allocation partial average approach/ B6150C Communication switching B6210L Computer communications
中文摘要	In existing deterministic core-stateless packet scheduling schemes, scalability is often achieved at the expense of under-utilization of the reserved bandwidth for flows at core nodes. This increases the burstiness in the traffic flow and limits the utility of network resources. The under-utilization is reduced by a core-stateless packet scheduling architecture, called the delay vector reference system. By using the virtual delay vector technique, the system provides the same end-to-end delay bound as VirtualClock and guarantees per-node accurate reserved rate allocation for each flow not just at edge nodes as with existing core-stateless schemes. Also, the system uses the partial average approach to meet a variety of accuracy and cost requirements. Additionally, these algorithms have good incremental deployability due to the similarity of operations at core nodes.
语种	中文 ; 中文
出版者	Tsinghua Univ. Press ; China
内容类型	期刊论文
源URL	[http://hdl.handle.net/123456789/9919]
专题	清华大学
推荐引用方式 GB/T 7714	Qin Yan,Xiang Yong,Shi Meilin. Virtual delay vector-based core-stateless packet scheduling architecture[J],2010, 2010.
APA	Qin Yan,Xiang Yong,&Shi Meilin.(2010).Virtual delay vector-based core-stateless packet scheduling architecture..
MLA	Qin Yan,et al."Virtual delay vector-based core-stateless packet scheduling architecture".(2010).

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