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Fast inductance and resistance extraction of 3-D VLSI interconnects based on the method of K element
Wei Hong-chuan ; Yu Wen-jian ; Yang Liu ; Wang Ze-yi
2010-05-06 ; 2010-05-06
关键词Practical Theoretical or Mathematical/ electric admittance electric resistance inductance integrated circuit interconnections matrix algebra VLSI/ fast inductance extraction fast resistance extraction 3-D VLSI interconnection K element method integrated circuit parasitic inductive effect localization property window selection technique filament partitioning admittance matrix multilayered interconnection/ B2550F Metallisation and interconnection technology B0210 Algebra
中文摘要In the integrated circuits with frequency above several GHz, parasitic inductive effect has greatly influenced the circuit performance, therefore requiring efficient algorithm for extraction of frequency-dependent inductance and resistance. Based on good localization property of the K element (inverse of the partial inductance method), a fast algorithm for interconnect inductance and resistance extraction is proposed in this paper. With an efficient window selection technique, filament partitioning, and two improvements on calculating filament inductance and inverting the global admittance matrix, complex structures of multilayered interconnects can be handled very well. While preserving good accuracy, the presented method exhibits about 100x speed-up over the FastHenry for some actual examples.
语种中文 ; 中文
出版者Chinese Inst. Electron ; China
内容类型期刊论文
源URL[http://hdl.handle.net/123456789/9831]  
专题清华大学
推荐引用方式
GB/T 7714
Wei Hong-chuan,Yu Wen-jian,Yang Liu,et al. Fast inductance and resistance extraction of 3-D VLSI interconnects based on the method of K element[J],2010, 2010.
APA Wei Hong-chuan,Yu Wen-jian,Yang Liu,&Wang Ze-yi.(2010).Fast inductance and resistance extraction of 3-D VLSI interconnects based on the method of K element..
MLA Wei Hong-chuan,et al."Fast inductance and resistance extraction of 3-D VLSI interconnects based on the method of K element".(2010).
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