QQ客服 官方微博 反馈留言

	A low-power high-speed divide-by-2/3 prescaler
	Wenjian Jiang; Fengqi Yu
	2016
会议名称	ICCSS2016
会议地点	Mexico
英文摘要	A novel low-power high-speed extended true singlephase clock-based (ETSPC) divide-by-2/3 prescaler is presented. Compared with the conventional topologies, one of the precharge stages in the ETSPC flip-flops is eliminated. Therefore, the number of switching stages is reduced to 5 and the total number of transistors is reduced to 13. The proposed and conventional prescalers are simulated in a standard 0.18- μm CMOS process. Simulation results show that compared with the conventional ETPSC based prescalers, 30%~61% and 25%~57% less power consumption in divide-by-2 and divideby- 3 mode, respectively, for 1.5-V power supply
收录类别	EI
语种	英语
内容类型	会议论文
源URL	[http://ir.siat.ac.cn:8080/handle/172644/10600]
专题	深圳先进技术研究院_医工所
作者单位	2016
推荐引用方式 GB/T 7714	Wenjian Jiang,Fengqi Yu. A low-power high-speed divide-by-2/3 prescaler[C]. 见:ICCSS2016. Mexico.

个性服务

查看访问统计

相关权益政策

暂无数据

收藏/分享

除非特别说明，本系统中所有内容都受版权保护，并保留所有权利。