Low-Power Design Of Ethernet Data Transmission

	Low-Power Design Of Ethernet Data Transmission
	Wen-Ming Pan; Qin Zhang; Jia-Feng Chen; Hao-Yuan Wang; Jia-Chong Kan
刊名	JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY
	2014
英文摘要	For the reliability and power consumption issues of Ethernet data transmission based on the field programmable gate array (FPGA), a low-power consumption design method is proposed, which is suitable for FPGA implementation. To reduce the dynamic power consumption of integrated circuit (IC) design, the proposed method adopts the dynamic control of the clock frequency. For most of the time, when the port is in the idle state or lower-rate state, users can reduce or even turn off the reading clock frequency and reduce the clock flip frequency in order to reduce the dynamic power consumption. When the receiving rate is high, the reading clock frequency will be improved timely to ensure that no data will lost. Simulated and verified by Modelsim, the proposed method can dynamically control the clock frequency, including the dynamic switching of high-speed and low-speed clock flip rates, or stop of the clock flip.
收录类别	其他
原文出处	http://d.wanfangdata.com.cn/periodical_zgdzkj-e201404006.aspx
语种	英语
内容类型	期刊论文
源URL	[http://ir.siat.ac.cn:8080/handle/172644/6261]
专题	深圳先进技术研究院_南沙所
作者单位	JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY
推荐引用方式 GB/T 7714	Wen-Ming Pan,Qin Zhang,Jia-Feng Chen,et al. Low-Power Design Of Ethernet Data Transmission[J]. JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY,2014.
APA	Wen-Ming Pan,Qin Zhang,Jia-Feng Chen,Hao-Yuan Wang,&Jia-Chong Kan.(2014).Low-Power Design Of Ethernet Data Transmission.JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY.
MLA	Wen-Ming Pan,et al."Low-Power Design Of Ethernet Data Transmission".JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY (2014).