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	Yield enhancement for 3D-stacked ICs: Recent advances and challenges
	Xu, Qiang; Jiang, Li; Li, Huiyun; Bill Eklow
	2012
会议名称	17th Asia and South Pacific Design Automation Conference (ASP-DAC)
会议地点	澳大利亚
英文摘要	Three-dimensional (3D) integrated circuits (ICs) that stack multiple dies vertically using through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The shift towards volume production of 3D-stacked ICs, however, requires their manufacturing yield to be commercially viable. Various techniques have been presented in the literature to address this important problem, including pre-bond testing techniques to tackle the “known good die” problem, TSV redundancy designs to provide defect-tolerance, and wafter/die matching solutions to improve the overall stack yield. In this paper, we survey recent advances in this filed and point out challenges to be resolved in the future.
收录类别	EI
语种	英语
内容类型	会议论文
源URL	[http://ir.siat.ac.cn:8080/handle/172644/3828]
专题	深圳先进技术研究院_集成所
作者单位	2012
推荐引用方式 GB/T 7714	Xu, Qiang,Jiang, Li,Li, Huiyun,et al. Yield enhancement for 3D-stacked ICs: Recent advances and challenges[C]. 见:17th Asia and South Pacific Design Automation Conference (ASP-DAC). 澳大利亚.

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