Low power design in 100 MHz embedded SRAM

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	Low power design in 100 MHz embedded SRAM
	Wang DH ; Qiu J ; Li YG ; Hou CH
	2001
会议名称	4th international conference on asic
会议日期	oct 23-25, 2001
会议地点	shanghai, peoples r china
页码	599-602
通讯作者	wang dh chinese acad sci inst semicond pob 912 beijing 100083 peoples r china.
中文摘要	low power design method is used in a 100mhz embedded sram. the embedded sram used in a fft chip is divided into 16 blocks. two-level decoders are used and only one block can be selected at one time by tristate control circuits, while other blocks are set stand-by. the sram cell has been optimized and the cell area has been minimized at the same time.
英文摘要	low power design method is used in a 100mhz embedded sram. the embedded sram used in a fft chip is divided into 16 blocks. two-level decoders are used and only one block can be selected at one time by tristate control circuits, while other blocks are set stand-by. the sram cell has been optimized and the cell area has been minimized at the same time.; 于2010-10-29批量导入; made available in dspace on 2010-10-29t06:36:41z (gmt). no. of bitstreams: 1 2854.pdf: 292819 bytes, checksum: 34d91cbd8ea62c1b88f2cec3e3db8425 (md5) previous issue date: 2001; chinese inst electr.; ieee beijing sect.; natl nat sci fdn china.; shanghai municipal sci & technol commiss.; chinese acad sci, inst semicond, beijing 100083, peoples r china
收录类别	CPCI-S
会议主办者	chinese inst electr.; ieee beijing sect.; natl nat sci fdn china.; shanghai municipal sci & technol commiss.
会议录	2001 4th international conference on asic proceedings
会议录出版者	ieee ; 345 e 47th st, new york, ny 10017 usa
会议录出版地	345 e 47th st, new york, ny 10017 usa
学科主题	微电子学
语种	英语
ISBN号	0-7803-6677-8
内容类型	会议论文
源URL	[http://ir.semi.ac.cn/handle/172111/13685]
专题	半导体研究所_中国科学院半导体研究所（2009年前）
推荐引用方式 GB/T 7714	Wang DH,Qiu J,Li YG,et al. Low power design in 100 MHz embedded SRAM[C]. 见:4th international conference on asic. shanghai, peoples r china. oct 23-25, 2001.